Software Development on an Intel XScale® Technology-Based Virtual Prototype

Abstract functional models allow an early start to the software development, but they need to be supplemented in order to ensure timing accuracy and consistency with the hardware models.

By Markus Wloka, Ph.D. and Guy Shaviv, Ph.D.

One major challenge in today’s embedded system-on-chip (SoC) designs is the ever-increasing amount of software, with more features and more interfaces to the underlying hardware. The use of mixed-level models in virtual prototypes helps developers address the increasing software demands by permitting parallel development of software and hardware. A pure functional-modeling approach poses concerns in regards to timing accuracy, yet timing-accurate models are too slow to run software effectively. What is needed is a blend of functional and timing accurate models that addresses timing-accuracy issues only where necessary.

Abstract functional models offer two distinct advantages for software development-simulation performance and early availability-both of which are a direct result of the modeling abstraction level. Simulation performance is crucial if a model is to run substantial amounts of software such as a modern operating system or a multimedia decoder. Early availability is important for launching software development early in the project timeline; software development tasks often are on the critical path for product release.

Although today’s model-development tools for pure functional models can enable the delivery of a full platform model within weeks, there are problems you cannot solve with only an abstract functional model that has no-or incomplete-timing information. The challenges include hardware or software tasks that depend on the timing, throughput, input rate, or other timing-related properties of a system. Fortunately, these development tasks do not need the entire model to be timing accurate. The model can introduce timing only where it is needed, and thereby reduce the level of abstraction only for a fraction of the system.

The ability to compose a mix of functional and timed models, often referred to as hybrid or mixed-level modeling, and the capability to efficiently simulate such a model become more and more vital for today’s SoC projects. Tight integration of tools that support timing-accurate modeling with functional models allows such hybrid modeling, and enables a methodology that lets designers make the trade-offs between performance and accuracy.

This integration also addresses another key requirement for software development: the ability to interface and work with common software debuggers. Software developers have different debugger preferences, so a mixed-level verification platform has to provide interfaces to multiple software debuggers, and these interfaces have to operate together with the debuggers in the hardware and verification domains.

Virtual Prototypes Require a Unified Verification Environment

While it is a great benefit to have an accurate functional model or virtual prototype for software development available early in the design cycle, and many months before the hardware design has been completed, it also comes with a certain risk. The functional model is built using the initial specification of the system. When architectures are being refined and the hardware (RTL) is being developed, changes may occur that affect that system specification. Therefore, the hardware and the functional model (used for software development) may get out of sync. This loss of sync might be due to bug fixes, changes in the structure, or any of several other reasons.

An inability to ensure the consistency of the actual hardware that is being developed with the functional model runs the risk that the software will not function properly once the hardware design has been completed. This defeats the purpose of concurrent hardware and software development. Hence, the modeling tool also needs to provide a verification environment that allows continuous integration of hardware and software. It is therefore mandatory to provide a common test and regression environment for the virtual prototype, mixed-level models, and the hardware platform to make sure these models are in sync.

A common test environment is possible if the test benches are designed to participate in both cycle-accurate verification and abstract functional model verification. This can be achieved by a layered design in which the core of the test bench is functional and an adapter layer lets it participate in cycle-accurate model verification. Assertions can then verify consistent behavior of the cycle-accurate and functional models when exercised by the test bench.

An example of such tools comes from a Synopsys-Virtio partnership that allows the use of System Studio, a SystemC™-based architecture design and analysis environment, as an integrated development environment for mixed-level modeling. In System Studio developers can assemble and simulate models at different and mixed levels of abstraction, including using Virtio’s functional models, dataflow models, C/C++/SystemC models, and RTL models. Transaction-level models are attached to functional models with interfaces containing timing information to tailor the hardware architecture to the requirements of its core applications, including bandwidth, throughput, latency and buffer sizes.

Virtual Prototypes for Intel XScale® Technology

Virtio offers several functional models for the Intel XScale microarchitecture that fit into the integrated tool set. The VPXS Virtual Platform, for instance, is a fast, full-function software emulation of the Intel® PXA250 Applications Processor development board. The Virtio VPXS-WM Virtual Platform is an architectural variant in which the Intel XScale core is enhanced with the Intel® Wireless MMX™ instructions.

Figure 1 illustrates where timing enhancements may be applied to a virtual prototype for a typical SoC architecture that includes an embedded Intel XScale technology-based processor, high-speed memory and networking units, and several lower-speed peripherals. In such a prototype, the Intel XScale core is modeled with an instruction-accurate instruction-set simulator (ISS) and all of the peripherals are implemented with functional models. Coupled to the functional models is a timed cycle-accurate model of the on-chip bus, written in SystemC using Synopsys’ System Studio.

Figure 1 - A mixed-level model uses functional modeling for most blocks, with timing-accurate modeling reserved for critical functions such as the processor bus. Transactors allow blocks to function either way, depending on test needs.

The SystemC bus model lies between the ISS and the functional models of the peripherals. The CPU is represented to the bus as a master component and all the functional peripheral models are represented to the bus as a slave component. The models connect with transactors to the on-chip bus. These transactors are responsible for converting transactions in one domain to the other. There are two types of transactors: Virtio to SystemC and SystemC to Virtio.

The cycle-accurate bus model takes control of simulation when a transaction is pending and receives updates with the simulation time before processing each transaction. To increase the performance, a switch allows disengaging the SystemC bus model for high-performance tasks, for instance booting an operating system, then engaging the SystemC bus model again for performing specific tests after the operating system is running.

Switching from an abstract functional model to a timed model requires a state transfer between the two models. This may not always be a simple task. It may not be easy to infer the state of the abstract model from that of the timed one. Also, the state of the abstract model may map to more than one state of the timed model. To resolve this problem, switching can happen only at times when the state of both models is known, such as when the bus is idle.

This level of integration allows developers to perform bus-analysis tasks during complex software operations such as booting Linux and running networking applications on top of it. For instance, they can measure utilization of the on-chip bus by connecting System Studio monitors to the simulation. Although performance can vary depending upon the particular SoC being modeled and the efficiency of the model code, typically results show that booting an operating system such as Linux happens at least 50 times faster with the functional model than with the timed, cycle-accurate bus model.

These mixed-level simulations, then, allow the development and debug of drivers, OS ports, and application software very early in the design cycle. Yet the models can be refined by adding more detailed information, such as cycle-accurate timing and RTL implementations. This ability also allows the models to remain concurrent with the hardware design. The result is that a mixed-level design and verification environment will speed up the design cycle for an Intel XScale technology-based embedded design, and will reduce the number of bugs in hardware and software.

Markus Wloka is Director of Research & Development (R&D) for the Synopsys Verification Group in Herzogenrath, Germany. He received his Vordiplom in Informatik from Christian-Albrechts-Universitaet, and an M.S.C. and a Ph.D. in Computer Science from Brown University. Guy Shaviv is the VP of Engineering at Virtio Corp and has over 15 years of hands-on experience in software development. Shaviv received his Ph.D. from the Technion - Israel Institute of Technology.