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Optimizing an Eight-Layer Flip Chip Package to Achieve 6.25GBps CEI SerDes Performance

By Jitesh Shah at IDT and Lisa Murphy at Ansoft

With increasing data rates in high-speed serializer/deserializer (SerDes) applications, each component of the channel — from the transmitter chip to the receiver chip — needs to be designed so that maximum energy is transferred without losses due to impedance discontinuities in the channel. This article presents a methodology to optimize one component of the channel (the transmitter package) using Time Domain Reflectometry (TDR) to determine the size and location of the impedance discontinuities, and optimizing the layout to minimize the discontinuities. The techniques used can be applied to other components in the channel, such as printed circuit board (PCB) vias, connectors and others. Commercially available two-dimensional (2-D) and three-dimensional (3-D) electromagnetic field simulators (Ansoft Q3D Extractor and Ansoft HFSS) and circuit simulator (Ansoft Designer) were used for this study.

Introduction

In a multigigabytes-per-second (GBps) regime, rise times in tens of picoseconds are not uncommon. The spectrum of signals can now extend into several gigahertz (GHz) where a package interconnect structure that used to be electrically transparent in the past starts affecting signal quality if not designed correctly. The package interconnect behaves as a distributed structure and has to be designed as a transmission line due to the relatively shorter signal wavelength. For maximum energy transfer, each transition within the package has to be carefully designed to minimize impedance discontinuities.

High-speed SerDes applications use a differential signaling technique where a pair of interconnects are used to transmit signal energy as opposed to a single interconnect. For the differential signal energy to be transmitted efficiently, the differential impedance a differential signal sees should be constant. Desired impedance for 6.25GBps CEI SerDes is 100Ω with package return loss not exceeding -8dB across the frequency bandwidth. If the channel has impedance discontinuities, a significant amount of signal energy could reflect back, hence possibly violating the return loss specifications.

Differential Impedance

The two lines of a differential pair are driven in odd-mode with equal magnitude and 180 out of phase with one another.

 

Circuit equations for each line in a coupled transmission line pair driven in odd-mode with inductive terms are shown below.

As shown in the above equation, the equivalent odd-mode inductance of each line is lower by the mutual inductance between the two lines.

Similarly, circuit equations for each line in a coupled transmission line pair driven in odd-mode with capacitive terms are shown below.

As shown in the above equation, the equivalent odd-mode capacitance of each line is higher by the mutual capacitance between the two lines.

Using the above relationships, the odd-mode characteristic impedance of each line can be defined as;

Therfore,

Hence, for a lossless coupled transmission system, these four quantities need to be optimized to meet the 50Ω odd-mode impedance for each line.

Package Modeling and Simulation

The package used for the study is an eight-layer flip chip package. The differential pair traces routed on the top layer is optimized to 100Ω differential impedance using the 2D feature of the Ansoft Q3D Extractor. The two possible sources of impedance discontinuities within the package are the bump-breakout or escape region from the die and via/solder ball region. Since rearranging die bumps and solder ball locations is usually not an option, these are always the hardest regions to control the impedance.

Package return loss specification defined for the 6.25 GBps CEI SerDes is -8dB across the entire spectrum. Although the specification is -8dB, the intent of this article is to demonstrate techniques to improve the return loss performance as much as possible without changing the die bump arrangement or the package pinout.

At the specified bit rate, signal rise times are in the range of 35ps. For digital signals with rise times typically defined as the 10 percent to 90 percent transition time of the signal, the knee-frequency where the envelope slope of the frequency-domain spectrum changes from -20dB/decade to -40dB/decade is approximately

This is going to be the frequency bandwidth used to design the package differential pair, that is, the return loss specification of -8dB should be met from DC to 10GHz.

A 3-D electromagnetic tool (Ansoft HFSS) is used to extract the frequency domain behavior of the interconnect structure. The tool solves Maxwell’s equations in the frequency domain using the Finite Element Method, where an initial mesh is generated in which the structure gets divided into thousands of tetrahedral elements. For an accurate solution, the tool uses an adaptive meshing technique in which the mesh is automatically refined in critical regions until a predefined solution criterion is achieved.

Figure 1 shows the return loss in dB from DC to 10GHz for the package differential pair. Return loss clearly exceeds -8dB for frequency components above 6GHz. Higher return loss is the result of impedance discontinuities in the package structure.

Figure 1. Package Differential Return Loss for the First-Pass Design

TDR is a convenient technique to evaluate the size, type (capacitive or inductive) and the location of the impedance discontinuities. Target odd-mode impedance of each line in the differential pair is 50Ω. If impedance exceeds 50Ω, the discontinuity is predominantly inductive and, if it is below 50Ω, the discontinuity is capacitive.

TDR analysis shows that the odd-mode impedance dips from 50Ω to 25Ω as the TDR pulse hits the core via/solder ball section of the differential pair. The negative dip signifies a capacitive discontinuity. Steps will be taken in the following sections to remove excess capacitance at the core via/solder ball region.

Optimizing the Layout

Figure 2 shows the E field distribution on layer 7 right above the solder ball pad. To remove the excess C, a hole in the ground plane is created above the ball pad slightly bigger than the ball pad diameter.

Fig 2. E Field Distribution on Layer 7 Above Solder Ball Pad

The separation between layer 7 and layer 6 is only 35um. Hence, although the excess C is removed by punching a hole on layer 7, coupling still exist between the ball pad and layer 6 (because of the relatively small distance). Layer 6 also happens to be the layer below the core via pad. Figure 3 shows the E field pattern on layer 6 because of the core via pad and the solder ball pad. A similar size hole as layer 7 is created on layer 6. Similar hole patterns are adopted for layer 2 and layer 3 above the core via pad in the top half of the flip chip substrate cross-section.

Fig 3. E Field Distribution on Layer 6 Above Solder Ball Pad and Below Core Via Pad

The via pad and barrel forms parasitic capacitance with power and ground planes around it as the differential trace transitions from layer 1 to layer 8 to connect to the solder ball. This excess capacitance adds to the overall capacitive discontinuity. Core and laser via clearance to the plane is increased by 50um each to reduce this parasitic capacitance.

Results for the Optimized Layout

Figure 4 shows the odd-mode impedance with each modification. The impedance magnitude steadily improves from a drop of 25Ω to 39Ω. The width of the discontinuity is also narrower with each subsequent modification. The overall discontinuity is still capacitive.

Figure 4. Impedance Profile for Each Subsequent Modification

Figure 5 shows the performance improvement of each modification in frequency domain. The return loss performance is significantly better than the first-pass design (approximately a 12.5dB improvement at 5GHz).

Fig 5. Package Differential Return Loss Performance Improvement with Each Modification

Conclusion

A methodology to optimize the high-speed SerDes layout in a package is shown using commercially available electromagnetic analysis and circuit simulation tools. The techniques presented are generic in nature, and can be applied to analyze and optimize other components of the channel.

 

About the Authors

Jitesh Shah is an advanced packaging engineer at Integrated Device Technology. Jitesh can be reached at jshah@idt.com.

Lisa Murphy is an application engineer at Ansoft. Lisa can be reached at lmurphy@ansoft.com