An ATCA based Home Subscriber System can Benefit from Multi-core ProcessorsBy Dan Leih, ATCA Product Marketing Manager – Embedded Computing, Emerson Network Power
The IP Multimedia Subsystem (IMS) provides an all IP architecture supporting the necessary core attributes to enable rich and demanding services to the subscriber. The Home Subscriber Server (HSS) is a centralized network database storing the subscriber profile information. This information is accessible by eligible network entities, predominantly the S-CSCF, to validate the subscriber and determine authorized service capabilities.
This application requires scalability and multiple compute resources, making the industry-standard AdvancedTCA® (ATCA®) technology an ideal platform. Multi-core processors are bringing increased compute performance to ATCA platforms but appropriate techniques must be applied to maximize the benefit of multi-core processors.
Figure 1: Emerson Centellis 3000 Series Communications Server
Constructing the HSS
Open communications servers based on ATCA technology are an ideal platform for an HSS, both technically and in terms of the total cost of ownership. Emerson ATCA communications servers address cost effectiveness through their broad range of integration options and an inherently scalable architecture, which enables network designers to "right size" their equipment. Increases in the transaction density over time enables further cost benefits without the need to replace the complete system. From a technical perspective, the key metrics to understand when analyzing the IMS HSS function are:
- the number of completed transactions per second, and
- the size of the subscriber database that can be constructed.
Figure 1 shows a Emerson Centellis 3600 series communications server. An HSS can be constructed using the following Emerson hardware:
- ATCA-F101 combined system controller and switching blade
- ATCA-7221 processor blade
- ATCA-S100 300GB storage blade
Support for legacy Home Location Register connection capability can be added using Emerson's ATCA-C110 AdvancedMC carrier blade with an Interphase iSPAN 3639 AdvancedMC Multiprotocol T1/E1/J1 Communications Controller.
The architecture of the HSS and a number of IMS functions is typically comprised of an array of front end and back end processor elements. The front-end server blades handle the subscriber transactions and signaling traffic from the network elements (i.e., the x-CSCF, SCIM and Application Servers1). The front-end processor blades operate as a single logical element, with any processor being capable of servicing any transaction for any subscriber.
The back-end server blades contain all the subscriber, application and network configuration data in a single X.500 directory. As with the front-end, use of a single logical database implemented across the back-end server blades allows the database to scale transparently by simply adding server blades.
Implementation of the HSS function on the Emerson Centellis 3000 series ATCA communications server supports N+M High Availability (HA) at the server blade element level as well as supporting geographical redundancy to mitigate catastrophic site-based failures.
The HSS is an excellent candidate for a Symmetric Multi-Processor architecture server blade. The Motorola ATCA-7221 processor blade features dual Intel® Xeon® processors with up to 32GBytes of SDRAM and 64-bit addressing capability. This blade provides the primary payload element required to build the HSS.
Estimates indicate that approximately 1200 HSS transactions-per-second can be serviced by the ATCA-7221 processor blade. This transaction-per-second rate scales in a near linear fashion via additional blades. Given an average subscriber record of 2.5Kbytes, a back end ATCA-7221 processor blade can be estimated to support 6.5 million subscribers. An ATCA chassis supporting 12 such blades would support in the region of 80 million subscribers. Emerson also offers a 16-slot chassis, leaving 14-slots per chassis for payload.
These estimates are for a situation where each subscriber has a distinct and separate data record. In reality there is commonality between subscriber records that could be exploited in order to reduce memory-per-subscriber requirements. Over time the amount of memory space per subscriber will grow as there is a trend to include more information in the subscriber data record. New data will include such information as a picture of subscriber and call plan records. This will drive up the memory requirements.
Because of its inherent multi-processor, multi-blade configuration, the HSS is an ideal application for a multi-core architecture. The introduction of multi-core processors from Intel provides developers with an opportunity to scale performance while optimizing power consumption. Initial efforts to port existing code to multi-core blades have produced inconsistent results in terms of performance. However, techniques to increase the performance of the HSS and other applications on multi-core devices are emerging and are now beginning to be deployed.
One technique is to "pre-process" data streams2. In this type of optimization, one core is used to identify the type of data being processed. A determination is then made about how to process the particular data stream. Depending on the type of processing and performance required a data stream may be "pinned" to a particular core or sent to the most available core using a load balancing technique. The objective with pre-processing is to control the activity of the cores rather than allow processing in a random fashion. Figure 3 illustrates this concept.
According to Intel3, increasing the amount of parallelism (or threading) in an application is key to maximizing performance in multi-core processors. To take full advantage of potential processor performance, developers must understand the inherent parallelism in their applications. Intel provides development tools and technical information to assist the developer in achieving maximum performance on multi-core platforms. Information is available on the Intel Web site.
Without software optimization many applications achieve comparable performance between multi-processor and multi-core implementations. However, telecom customers are beginning to report results of increased performance when moving from dual processor to early dual core implementations. That this increase in performance takes place within the 200 Watt ATCA power envelope is a key benefit of multi-core processing.
Leading vendors of multi-core processors understand the need to optimize code and support their customers with tools and libraries to make this transition easier. To assist developers in identifying opportunities for parallelism within the application, Intel offers a variety of tools including Intel® C++ Compiler 9.0 for Linux, Intel® VTune Performance Analyzer, Intel® Thread Checker, and others.
The communications server is an excellent platform for service layer functions such as the HSS. Use of a common platform based on ATCA standards enables scalability in high availability configurations. Scaling can be easily accomplished by adding computing capability and memory via blades without the need to re-architect the system.
The move to multi-core processors delivers performance improvement opportunities. In order to take advantage of these performance gains, analyzing the parallelism of application software is recommended. The software tools that Intel has created can ease this transition, helping to ensure the application can be optimally tuned for the hardware that powers it.
With ATCA based systems such as Emerson's Centellis 3000 series communications servers, designers can maximize efficiency of their design teams and produce the broadest range of functions with the least amount of redesign, enabling a higher percentage of design time to be spent on revenue-generating applications.
1 IMS HSS Application Example: An IMS Home Subscriber Server built on an AdvancedTCA
Communications Server, Dan Leih & Dave Halliday, Emerson Network Power
2 Future directions for Modular Communications Platforms, Lynn Comp, Intel® Leap Ahead Forum, February 2007
3 Optimization Techniques for Intel® Multi-Core Processors, Max Domeika and Lerie Kane, Intel