Intel Tips 22nm SoC Recipes, 14nm Process

Seeking to extend its technology lead, Intel Corp. disclosed its recipes to enable 22nm system-on-a-chip (SoC) devices and also provided a glimpse of its 14nm process.

Already looking to ramp up its 22nm process, Intel is also moving full speed ahead to develop a 14nm technology. The chip giant plans to extend its vertical tri-gate transistor structure to the 14nm node, according to a roadmap presented by Mark Bohr, Intel senior fellow and director of process architecture and integration.

The 14nm node will also incorporate strained silicon, a high-k/metal-gate scheme and other features, Bohr said during a presentation at the Intel® Developer Forum (IDF) in San Francisco.

Other companies, including IBM, GlobalFoundries and TSMC, are also pursuing 3-D transistors or finFETs for the 14nm node. Intel plans to begin ramping up its 14nm process by the fourth quarter of 2013, Bohr said. In doing so, Intel will have a “four year lead in tri-gate technology,” he said.

Bohr did not provide further details about its 14nm technology, but he reiterated the company’s previous position that extreme ultraviolet (EUV) lithography will not be ready in time for the 14nm node. In previous reports, Intel said it plans to extend traditional 193nm optical lithography down to 14nm, with the help of quintuple patterning and other techniques.

“We would like to use EUV, but it’s not ready,” Bohr said in an interview. “I’d like to have EUV” ready for the 10nm node.

It is also unlikely that 450mm technology will be ready-at least for the early stages of the 14nm node, analysts said. Intel, Samsung and TSMC are aggressively pushing for 450mm fabs, but it’s unclear if the equipment makers can deliver the tools in time for 14nm, analysts said.

During the presentation, Bohr also described Intel’s recently-announced 22nm technology. In May, the chip giant rolled out a vertical tri-gate transistor technology at the 20nm generation node.

Intel’s 3-D transistor design represents a fundamental departure from the two-dimensional planar transistor structure. The first processor based on the technology is code-named “Ivy Bridge.” Ivy Bridge is slated for high-volume production readiness by the end of this year.

A large part of Bohr’s presentation was devoted to the benefits of a vertical tri-gate transistor at the 20nm generation, as compared to the traditional planar structure at that node. Technologists at GlobalFoundries recently insisted planar, rather than finFET, transistors are the best fit for foundry customers at the 20nm technology generation.

In response, Bohr said Intel’s tri-gate structure enables a “10X reduction in leakage” over planar devices. Compared to tri-gate structures, "22nm planar transistors would provide only a modest improvement in delay verses voltage," he said. “Tri-gate transistors provide an unprecedented 37 percent delay improvement at low voltage,’’ as opposed to 32nm planar structures.

Bohr also discussed Intel’s SoC process recipes for the 22nm node. In previous years, Intel developed a standard “one-size-fits-all” CPU process technology for a particular node.

Starting at the 32nm node, Intel developed a CPU (P1268) and SOC (P1269) process. The CPU and SoC processes have identical feature sets, but the SoC version incorporates a set of recipes specifically for device designers.

For example, Intel will provide a standard CPU process at 22nm, internally called P1270. Based on a tri-gate transistor structure, the CPU process incorporates high-speed logic circuits and interconnects.

The SoC version, dubbed P1271, makes use of a low leakage technology, dense interconnects and passives. It will also include 1.2V low-power and 1.8V thick-gate options.

Intel will provide some four SoC recipe options for designers: high-performance, standard performance, low power and ultra low power, according to Bohr.

The technology is aimed for a range of applications, including the booming mobile space. Intel is seeking to propel its x86-based processors in the mobile space-and displace the ARM camp in the process.

Intel’s first 22nm processor, called Ivy Bridge, is mainly geared for desktops and possibly higher-end notebooks. The next 22nm processor is codenamed Haswell, which is tailored for Ultrabooks. Developed by Intel, Ultrabooks is a new class of portables that are aimed at the tablet PC market.

At IDF, Intel described the new class of platform power management in development for the 2013 “Haswell” products for Ultrabooks. Haswell is said to reduce idle platform power by more than 20 times over current designs, according to Intel.

Mark LaPedus has covered the semiconductor industry since 1986, including five years in Asia when he was based in Taiwan. He has held senior editorial positions at Electronic News, EBN and Silicon Strategies. In Asia, he was a contributing writer for Byte Magazine. Most recently, he worked as the semiconductor editor at EE Times.